A Reusability-Aware Cache Memory Sharing Technique for High Performance CMPs with Private L2 Caches

For high-performance chip multiprocessors (CMPs) to achieve their maximum performance potential, an efficient support for memory hierarchy is important. Since off-chip accesses require a long latency, high-performance CMPs are typically based on multiple levels of on-chip cache memories. For example, most current CMPs support two levels of on-chip caches. While the L1 cache architecture of these CMPs is almost same, the L2 cache organization is quite different. All the processors in the CMP may share the same L2 cache or each processor may have its own private L2 cache. While a private L2 cache has a short access time, a shared L2 cache can better adapt to varying memory requirements of each processor. In this paper, we propose an on-chip L2 cache organization which takes advantage of both a private L2 cache and a shared L2 cache. In skeleton, our L2 cache organization is based on a private L2 cache organization which has the short access latency. When a cache block in the private L2 cache is selected for an eviction, our proposed organization first evaluates the reusability of the cache block. If the cache block is likely to be reused, we save the evicted cache block in one of peer L2 caches which may have efficiently invalid blocks. By selectively writing evicted cache blocks to peer L2 caches, the proposed L2 cache organization can effectively simulate a shared L2 cache. Experimental results using a CMP simulator showed that the proposed L2 cache organization improved the average memory latency by 14% on average over a pure private L2 cache organization for the SPLASH2 benchmark programs.